1. Field of the Invention
The present invention relates to a cell hierarchy verification method and apparatus for an LSI layout and, more particularly, to a cell hierarchy verification method and apparatus for verifying and correcting the hierarchical layout of cell figures forming a gate array LSI layout.
2. Description of the Prior Art
Technical terms used in the description of the present invention will be first explained.
"LSI layout" is a cluster of one or more cells which are hierarchically described.
Figures in the cells of the LSI layout are classified into "diffusion figures" and "polysilicon figures" forming transistors and "wiring figures" connecting the transistors. These figures can be discriminated from each other by integral numbers called layer numbers.
"Cell" represents a processing unit consisting of one or a plurality of necessary figures. Each unit cell has "origin" independent of other cells, and "name" for discriminating the cell from other cells. The discrimination name added to each cell is particularly called "cell name".
"Cell references figure" means that enough information to represent attributes in a cell such as a figure shape, layout position, and layer number is stored in a predetermined format using the cell origin as a reference.
"Hierarchically described" means that the references of cells are sequentially described using one reference cell as a top. A reference cell serving as a top is particularly called "top cell". A referencing cell is called "parent cell", and a referenced cell is called "child cell". A last-stage cell, which can be reached by sequentially traversing child cells from a specific cell, e.g, a first-stage cell (parent cell), is called "descendant cell of first-stage cell".
Each layout figure pattern (to be simply referred to as a figure hereinafter) forming a transistor will be described.
FIG. 7 is a perspective view schematically showing a conventional LSI layout in which figures forming a transistor in the manufacturing process are vertically separated. In FIG. 7, reference numeral 101 denotes a polysilicon figure; and 102, a diffusion figure. The polysilicon and diffusion FIGS. 101 and 102 are laid out so as to divide the diffusion FIG. 102 into two, right and left regions by the polysilicon FIG. 101.
FIG. 8A is a perspective explanatory view three-dimensionally schematically showing the structure of a transistor manufactured based on an LSI layout using the figure layout in FIG. 7. FIG. 8B shows symbols set in advance in order to represent the circuit arrangement. In FIG. 8A, the transistor is roughly comprised of a polysilicon wiring layer 111, a gate 112, and a pair of diffusion regions 113 and 114.
The polysilicon wiring layer 111 is formed in correspondence with the polysilicon FIG. 101, and the gate 112 is formed in correspondence with the portion where the polysilicon and diffusion FIGS. 101 and 102 overlap each other. The diffusion regions 113 and 114 are formed in the remaining portions in the diffusion FIG. 102 that are divided by the overlapping portion with the polysilicon FIG. 101.
As is well known, the gate 112, and a portion 115 between the diffusion regions 113 and 114 are subjected to predetermined processing in order to electrically connect the diffusion regions 113 and 114 upon current supply to the polysilicon wiring layer 111.
That is, these portions 111 to 114 construct one objective transistor.
The schematic arrangement of a cell hierarchy verification apparatus for a conventional LSI layout will be described with reference to FIGS. 1 to 13.
FIG. 1 is a block diagram showing the schematic arrangement of a conventional cell hierarchy verification apparatus. In FIG. 1, the conventional apparatus comprises an input data section 1a having each input data registered in advance in a memory unit such as a hard disk, an input device 2 such as a keyboard or a mouse for instructing apparatus operation, a data processor 3a which operates under program control, a memory section 4a such as a memory on a computer, an output data section 5a for outputting verification data to a memory unit such as a hard disk, and a verification section 6a for verifying LSI layouts using verification data and appropriately outputting the verification results.
The input data section 1a includes each individual data such as a top cell name 11, a function block cell name 12, and LSI layout data 13. The data processor 3a comprises an input unit 31 for reading necessary data from the input data section 1a in correspondence with an operation instruction from the input device 2, a mapping unit 35 for mapping data for each function block cell, and an output unit 34 for outputting a mapped LSI layout.
The memory section 4a comprises a general-purpose memory unit 41 for temporarily storing each data read by the input unit 31, and a cell memory unit 46 used for cell mapping.
The output data section 5a includes LSI layout verification data 53 output upon mapping. The verification section 6a comprises an appropriate verification means 62 for verifying hierarchy on the basis of the LSI layout verification data 53, and outputs corrected verification result data and the like.
The operations of the respective building sections in the conventional apparatus will be described.
Upon reception of an instruction from the input device 2, the input unit 31 of the data processor 3a sequentially loads corresponding data from the input data section 1a, and temporarily stores them in the general-purpose memory unit 41 of the memory section 4a. The mapping unit 35 checks whether a cell to be processed is present for all cells each having a top cell name or a function block cell name stored in the general-purpose memory unit 41, and maps cells to be processed one by one in accordance with an operation flow shown in FIG. 2 (step D1). Mapping in step D1 for the cells to be processed is performed in accordance with an operation flow shown in FIG. 3.
Referring to FIG. 3, in step E1, cell data are loaded from the general-purpose memory unit 41 and temporarily stored in the cell memory unit 46. In step E2, as shown in FIG. 4, the cell data in the cell memory unit 46 are sequentially read out from the first one. Processing of "if the readout data is figure data, sending it to the output unit 34, erasing it from the cell memory unit 46, and reading out the next data" is repeatedly performed until all the stored data are processed.
If the readout data is cell reference information in step E2, whether the cell name is a function block cell name stored in the general-purpose memory unit 41 is checked in step E3. If NO in step E3, corresponding cell data is loaded via the input unit 31. In step E4, the coordinate values of the data are transformed into coordinates on the parent cell, and the resultant data is additionally stored at the final address in the cell memory unit 46. If YES in step E3, the reference information is directly sent to the output unit 34 without retrieving the cell contents.
The output unit 34 receives the respective LSI layout data from top cell data in units of function block cell data. The output unit 34 outputs the data to the output data section 5a. The output data section 5a sequentially stores the mapped data as LSI layout verification data 53 in a memory unit such as a hard disk. The LSI layout verification data 53 are sent to the verification section 6a and appropriately verified by the verification means 62. As a result, data substantially corrected by the verification results are output.
The operation of the conventional apparatus will be explained using detailed input data.
FIG. 5 is an explanatory view showing an example of the cell hierarchical structure of input data in the conventional apparatus. In this example, a top cell name corresponds to bold-line cell A, and function block cell names correspond to bold-line cells B, E, and F. In the cell hierarchical structure in FIG. 5, top cell name A and function block cell names B, E, and F are designated via the input device 2 in accordance with LSI layout file names as input data.
Input data loaded to the input unit 31 of the data processor 3a are temporarily stored in the general-purpose memory unit 41 and mapped in order from cells A, B, E, and F (step D1). In step D1, during processing for top cell A, figures forming the cell are sequentially mapped by the mapping unit 35, and the mapped figures are sent to the output unit 34 (step E2). When data processing in step E2 progresses to reference information of cell C as a child cell for top cell A, it is determined in step E3 that cell C is not a function block cell. The processing therefore advances to step E4, and the figure data of cell C is coordinate-transformed into figure data of cell A as a parent cell. Similarly, reference information of cell F within cell C is temporarily transformed into coordinate values on cell A. The resultant data are registered in the cell memory unit 46.
When processing in the loop of step E2 progresses to reference information of function block cell B and reference information of function block cell F, it is determined in step E3 that cells B and F are "function block cells". The pieces of reference information are directly sent to the output unit 34. In this manner, in processing for top cell A, cell C is erased, while function block cells B and F are left.
Similarly, in mapping for function block cell B, cell D is mapped, and function block cell E is left. In mapping for function block cell E, both cells G and H are mapped. Data of function block cell F are directly output because there is no reference cell.
The output unit 34 outputs each received data as one data file. By referring to the LSI layout verification data 53 output from the output unit 34, a cell hierarchical structure comprised of cells A, B, E, and F can be obtained, as shown in FIG. 6.
A gate array LSI layout based on an LSI layout having the above transistor arrangement will be explained.
FIG. 9 is an explanatory view showing the features of the gate array LSI layout. Referring to FIG. 9, the cell hierarchy of the gate array LSI layout can be divided into an underlying cell portion 121 and an overlying cell portion 122 at the boundary of a given hierarchical layer. The underlying and overlying cells 121 and 122 have no parent-child relationship.
As shown in FIG. 10, the underlying cell 121 references cells including the polysilicon Figures 101 and the diffusion Figures 102 forming transistors, and cells including wiring Figures 103 for supplying power to transistors using a predetermined array representation.
As is apparent from FIG. 10, "array representation" is a representation method in which the data amount is effectively reduced by representing figures or cells as "xn figures or cells in the x direction at an interval w, and ym figures or cells in the y direction at an interval h".
For example, when n x m figures or cells are to be laid out in the x and y directions, if no array representation is employed, information corresponding to
[information on one figure or cell] x n x m is inevitably required. However, if data are stored using an array representation, any increase in number of figures or cells to be laid out requires only four kinds of requirements, i.e., the interval w and the number xn in the x direction and the interval h and the number ym in the y direction. As a result, information can be reduced to PA1 [information on one figure or cell] 4
In this case, figures forming transistors and figures for supplying power are not referenced one by one by an array representation. Instead, as shown in the gate array LSI layout in FIG. 10, a set of figures forming one or a plurality of transistors are described on one cell, and this cell is referenced by an array representation. Power supply wiring figures are described in a cell describing transistors, or defined in another cell and referenced by an array representation.
As shown in FIG. 11, cells 132 called function blocks are laid out to overlap the layout of cells 131 including transistor figures referenced by an array representation. In each function block cell 132, the polysilicon and diffusion Figures 101 and 102 for transistors, and wiring Figures 103 for connecting power supply wiring layers to each other and/or transistors to power supply wiring layers are described, as shown in FIG. 12. As upper cells, wiring Figures 133 for connecting the function block cells 132 are similarly described, as shown in FIG. 13.
However, the cell hierarchy verification apparatus for a conventional gate array LSI layout having the above arrangement suffers the following problems.
First, in the conventional gate array LSI layout, it is impossible to map all cells from a top cell and verify the layout.
This is because an underlying cell is compressed and referenced by an array representation in order to reduce the data size in a memory unit such as a hard disk, and all array representations must be mapped to verify the layout, which requires a larger memory capacity of the memory unit used in the program, resulting in a verification failure.
Second, the conventional gate array LSI layout cannot be verified by hierarchical processing for each cell at the boundary of a function block cell.
This is because the function block cell includes only wiring figures for connecting transistors to each other, and a connection error between a wiring figure and an underlying cell which are automatically laid out cannot be verified by verification for each function block cell.